QUESTA LINT SEMINAR
HOW TO KEEP YOUR HDL CODE PROPER AND HIGHER QUALITY FROM THE BEGINNING?
During FPGA/ASIC design flows, it is highly appreciated to cut the project budgets, get stuck on scheduling (for timely signoff), and proceed to the next step by correcting wrongly and inefficiently entered RTL code as early as possible (shift left). It is also worth reminding ourselves that most of the project engineering effort is spent during verification, so a clear RTL code would facilitate these verification steps.
Just at this point, as an integral part of Questa verification solutions, Questa Lint takes place and performs periodic/automated "static code" runs. It provides a modern, powerful (Visualizer) debugger and lets you generate clean and understandable RTL quality reports. As a member of Questa Verification Solutions, it requires no test bench. Still, it takes only RTL code and the same compiled code used by QuestaSim (constraints and UPF data where necessary).
Each time new RTL code is submitted to the design repository, it is a good practice to run static code analysis to ensure that the overall RTL design quality remains as expected. However, it might not be practical to do this over and over manually. To overcome this, integrating Questa Lint within a new trend called CI (continuous Integration) will help the design team automate the Questa Lint runs triggered by predefined steps.
In this session, the audience will be introduced to the general functionalities of Questa Lint, its static check rules contents, predefined and custom analysis methodologies, and how it complements other Questa verification tools. In the final stage, Questa Lint GUI and automatic triggering of the instrument within a continuous integration environment will be discussed.