FPGA/ASIC DESIGN, VERIFICATION AND SYNTHESIS
Rich portfolio of products with proven track of success, leverages your front-end and back-end design flows including design entry, verification, synthesis, place-and-route, physical verification and signoff for both ASIC and FPGA flows.
At some phases in the flows (verification, testing, custom IC tools etc...), the user has the freedom to choose the more convenient solutions for his/her needs.
In FPGA and ASIC design entry processes, there are products that facilitate the work of users and that new technologies are constantly adapted. It comes with a set of modules that make it easy to use design input with a graphical interface, compatibility with modern hardware description languages such as SystemC, SystemVerilog, advanced verification technologies such as UVM (SystemVerilog Assistant, Register Assistant, DesignChecker etc...).
Thanks to the simulators (ModelSim, Questa), validation IP libraries (Questa VIP), verification process management solutions and hardware-based verification devices i.e. emulators (Veloce, ProFPGA), which attract a great deal of attention in the industry, it is a very wide and self-contained verification process from relatively simple-scale projects to complex UVM-based verification processes. A proven portfolio is presented.
In projects where criteria such as reliability and area/power/performance optimizations are prioritized, solutions that can provide high quality synthesis outputs come to the fore. The synthesizers in the Sieemns EDA portfolio, besides optimized outputs, support high-end nodes on the ASIC side by collaborating with many chip manufacturers in the industry. In addition, "design packages" of relatively mature technology nodes are offered to design teams at relatively affordable prices.