Questa Verification & Simulation
Questa Verification is the first verification platform with a UVM-aware debug solution that provides engineers essential information about the operation of their dynamic class-based testbenches in the familiar context of source code and waveform viewing.
The Questa verification solution is an assemblage of technologies, methodologies, and libraries for modern ASIC and FPGA designs. Questa continues to evolve in response to the growing complexity of SoC designs.
Questa Advanced Simulator
Combines high performance, high capacity simulation with unified debug and functional coverage for complete native support of Verilog, SystemVerilog, VHDL, SystemC, SVA, UPF and UVM.
The industry’s most advanced portable stimulus testbench automation solution, achieving coverage goals 10 to 100X faster than constrained random testing and scaling across all design levels.
Questa Power-Aware Simulator
Power-aware simulation automatically verifies architecture and behavior of active power management structures in RTL and gates early in design flows to achieve optimal power reduction at least cost.
Questa Verification Management
A shared platform and environment for comprehensive verification management of design process, tools and data within a scalable, modular solution.
Simplifies, automates and enables requirements traceability from specification of hardware through HDL coding, implementation and validation.