Questa Clock-Domain Crossing
Designers use advanced multi-clocking and reset signal distribution architectures to meet high performance, low latency and low power requirements. Questa CDC and RDC tools focus on interactions between clock- or reset-domains that cannot be dealt with using simulation-based verification techniques.
Questa Clock-Domain Crossing (CDC) Verification
Questa CDC finds errors using structural analysis to detect clock-domains, synchronizers, and low power structures via the UPF. It then generates assertions and metastability models for protocol and reconvergence verification.
Questa Reset-Domain Crossing
Questa RDC formally verifies reset-domain crossings to exhaustively identify reset-domain crossing issues in SoC and system designs.
Questa Signoff CDC
Questa Signoff CDC automatically generates and analyzes assertions to rapidly identify chip-killing glitches and other clock-domain crossing issues.