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  • Advanced Code Coverage

ModelSim’s advanced code coverage capabilities provide valuable metrics for systematic verification and ease of use lowers the barriers for leveraging verification resources. All coverage information is stored in the highly efficient UCDB database. Coverage results can be viewed interactively, post-simulation, or after a merge of multiple simulation runs.

  • Mixed HDL Simulation

Comprehensive support of Verilog, SystemVerilog for Design, VHDL, and SystemC provide a solid foundation for single and multi-language design verification environments. An easy-to-use and unified debug and simulation environment provide FPGA designers the advanced capabilities they need.

  • Intuitive Debug Environment

ModelSim eases the process of finding design defects with an intelligently engineered debug environment that efficiently displays design data for analysis and debug of all languages. A broad set of intuitive capabilities for Verilog, VHDL and SystemC make it the ideal choice for ASIC and FPGA design.


ModelSim simulates behavioral, RTL and gate-level code, delivering increased design quality and debug productivity and platform-independent compile with outstanding performance. Single Kernel Simulator technology enables transparent mixing of VHDL and Verilog in one design.

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