Catapult High-Level Synthesis
Providing class-leading products and methodology for High-Level design, Siemens delivers solutions at multiple points of the design process. Design Checking, Code and
Functional Coverage and Formal verification for C++ and SystemC equivalence
Catapult Design Checker
Lint and formal analysis to validate your HLS designs for correctness before synthesis. Avoid design problems and QoR issues that can occur when coding for HLS.
Provides HLS-aware code coverage, including statement, branch, FEC, toggle and array access coverage. SV-inspired functional coverage with support for covergroups, coverpoints, bins and crosses.
Check the correctness of RTL against your High-Level models using SLEC. Enabling proof that specification and implementation are identical despite differences in language, timing, or abstraction.