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  • Place-and-route technology for complex SoC designs

Aprisa offers complete functionality for top-level hierarchical design and block-level implementation for complex digital IC designs. The detailed-route-centric architecture and hierarchical database enable fast design closure and optimal quality of results at a competitive runtime.

  • Detailed-Route-Centric Architecture

The detailed-route-centric architecture enables efficient and frequent communication between placement optimization, CTS optimization, and detailed routing for improved quality-of-results, reduced iterations, and 2X faster design convergence than the competition.

  • Specialized for Advanced Nodes

Leading foundry certified for advanced nodes. Innovative technologies, such as native color-aware MPT routing, Sibling Routing, congestion-aware low-resistance routing, and IR-aware and EM-aware place-and-route help to mitigate design challenges and deliver highest quality of results at advanced nodes.

  • PowerFirst Place-and-Route for Low Power

The PowerFirst place-and-route methodology ensures that low power is considered as a primary design target while meeting timing constraints. Advanced technologies such as path-based timing analysis and optimization, low power CTS, and dynamic power-driven P&R, help to meet the demanding low power requirement of modern SoCs.

Aprisa Place-and-Route

Designing at advanced process nodes requires a new place-and-route paradigm to manage the increasing complexity. Aprisa is a route-centric physical design platform for the modern SoC.

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